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ST8016T
COM/SEG LCD Driver
Preliminary
Note: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. This is not a final specification. Some parameters are subject to change.
Datasheet
Version 0.12 2007/10/29
ST8016T
1
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FEATURES
Number of LCD drive outputs: 160 Supply voltage for LCD drive: +15.0 to +30.0 V Supply voltage for the logic system: +2.5 to +5.5 V Low power consumption Low output impedance (Segment mode) Shift clock frequency - 20 MHz (MAX.): VDD = +5.0 0.5 V - 15 MHz (MAX.): VDD = +3.0 to + 4.5 V - 12 MHz (MAX.): VDD = +2.5 to + 3.0 V 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin Automatic transfer function of an enable signal Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 160 bits of input data Line latch circuits are reset when /DISPOFF active (Common mode) Shift clock frequency: 4 MHz (MAX.) Built-in 160-bit bi-directional shift register (divisible into 80 bits x 2) Available in a single mode (160-bit shift register) or in a dual mode (80-bit shift register x 2) - Y1->Y160 Single mode - Y160->Y1 Single mode - Y1->Y80, Y81->Y160 Dual mode - Y160->Y81, Y80->Y1 Dual mode The above 4 shift directions are pin-selectable Shift register circuits are reset when /DISPOFF active
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DESCRIPTION
The ST8016T is a 160-output segment/common driver IC suitable for driving large/medium scale dot matrix LCD panels, and is used in personal computers/work stations. The ST8016T is good both as a segment driver and a common driver, and it can create a low power consuming, high-resolution LCD.
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3
BLOCK DIAGRAM
V0R V12R V43R VSS Y1 Y2 Y159 Y160
FR /DISPOFF
LEVEL SHIFTER
VSS 160-BIT 4-LEVEL DRIVER 160 V43L V12L V0L
EIO1 EIO2
ACTIVE CONTROL
160-BIT LEVEL SHIFTER 160 160-BIT LINE LATCH/SHIFT REGISTER 16
8 BIT DATA LATCH
16
16
LP XCK
CONTROL LOGIC 8
L/R MD S/C SP CONVERSION & DATA CONTROL (4 to 8 or 8 to 8)
DATA LATCH CONTROL
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
VDD
VSS
4
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK
FUNCTION In case of segment mode, controls the selection or non-selection of the chip. Following an LP signal input, and after the chip selection signal is input, a selection signal is generated internally until 160 bits of data have been read in. Active Control Once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. In case of common mode, controls the input/output data of bi-directional pins. In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel input SP Conversion mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel input mode & Data Control in latch circuit; after that they are put on the internal data bus 8 bits at a time. In case of segment mode, selects the state of the data latch which reads in the data bus Data Latch Control signals. The shift direction is controlled by the control logic. For every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. In case of segment mode, latches the data on the data bus. The latch state of each LCD drive output pin is controlled by the control logic and the data latch control; 160 bits of data are Data Latch read in 20 sets of 8 bits. In case of segment mode, all 160 bits which have been read into the data latch are Line Latch/ simultaneously latched at the falling edge of the LP signal, and are output to the level shifter Shift Register block. In case of common mode, shifts data from the data input pin at the falling edge of the LP signal. Level Shifter The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to the driver block. Drives the LCD drive output pins from the line latch/shift register data, and selects one of 4 4-Level Driver levels (V0, V12, V43 or VSS) based on the S/C, FR and /DISPOFF signals. Controls the operation of each block. In case of segment mode, when an LP signal has been input, all blocks are reset and the control logic waits for the selection signal output from the Control Logic active control block. Once the selection signal has been output, operation of the data latch and data transmission is controlled, 160 bits of data are read in, and the chip is non-selected. In case of common mode, controls the direction of data shift.
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5
PIN DESCRIPTION (TCP TYPE)
DESCRIPTION LCD drive output Power supply for LCD drive Power supply for LCD drive Power supply for LCD drive Display data shift direction selection Power supply for logic system (+2.5 to +5.5 V) Segment mode/common mode selection Input/output for chip selection at segment mode EIO2, EIO1 I/O Shift data input/output for shift register at common mode DI0-DI6 I Display data input at segment mode DI7 I Display data input at segment mode/Dual mode data input at common mode XCK I Clock input for taking display data at segment mode /DISPOFF I Control input for output of non-select level I Latch pulse input for display data at segment mode/ LP Shift clock input for shift register at common mode FR I AC-converting signal input for LCD drive waveform MD I 4 or 8 bits mode selection input VSS P Ground (0 V) TEST1,TEST2 I Connect to GND or floating PS : Detail size see TCP drawing data SYMBOL Y1-Y160 V0L, V0R V12L, V12R V43L, V43R L/R VDD S/C I/O O P P P I P I
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6
INPUT/OUTPUT CIRCUITS
V DD
I
To Internal Circuit Applicable Pins L/R , S/C , DI6~DI0 , /DISPOFF , LP , FR , MD
GND (0V)
Figure 1 Input Circuit (1)
V DD
I
To Internal Circuit Applicable Pins DI7 , XCK
Control Signal
Vss (0V)
Vss (0V)
Figure 2 Input Circuit (2)
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V DD
I/O
To Internal Circuit Control Signal
GND (0V)
GND (0V)
VDD
Output Signal Application Pins EIO1 , EIO2
Control Signal GND(0V) Figure 3 Input/Output Circuit V0 V0 Control Signal 1 Control Signal 2 V12
O
Control Signal 3 GND(0V) V43 GND (0V) VSS
Control Signal 4
Application Pins Y1~Y160
Figure 4 LCD Drive Output Circuit
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7
7.1
FUNCTIONAL DESCRIPTION
Pin Functions
FUNCTION Logic system power supply pin Y Connected to +2.5 to +5.5 V. Ground pin Logic system power ground pin Y Do not short LGND with GND and Vss by ITO on LCD panel Y Connect it to GND on PCB or FPC. Connect to GND by ITO on LCD panel. Bias power supply pins for LCD drive voltage Y Normally use the bias voltages set by a resistor divider Y Ensure that voltages are set such that VSS < V43 < V12 < V0. Y ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin Input pins for display data Y In 4-bit parallel mode, DI3-DI0 are the display data input pins, and DI7-DI4 must be connected to LGND or VDD. Y In 8-bit parallel mode, All DI7-Dl0 pins are the display data input pins. Y Refer to section 7.2.2. Clock input pin for taking display data Y Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data Y Data is latched at the falling edge of the clock pulse. Input pin for selecting the reading direction of display data Y When set to LGND level "L", data is read sequentially from Y160 to Y1. Y When set to VDD level "H", data is read sequentially from Y1 to Y160. Y Refer to section 7.2.2. Control input pin for output of non-select level Y The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Y When set to LGND level "L", the LCD drive output pins (Y1-Y160) are set to level Vss. Y When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is canceled the driver outputs non-select level (V12 or V43), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, it cannot output the reading data correctly. Y Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform Y The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Y Normally it inputs a frame inversion signal. Y The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. Y Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. Mode selection pin Y When set to LGND level "L", 4-bit parallel input mode is set. Y When set to VDD level "H", 8-bit parallel input mode is set. Y Refer to section 7.2.2. Segment mode/common mode selection pin Y When set to VDD level "H", segment mode is set. Input/output pins for chip selection Y When L/R input is at LGND level "L", ElO1 is set for output, and EIO2 is set for input. Y When L/R input is at VDD level "H", ElO1 is set for input, and EIO2 is set for output. Y During output, set to "H" while LP * XCK is "H" and after 160 bits of data have been read, set to "L" for one cycle (from falling edge to failing edge of XCK), after which it returns to "H". Y During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is Page 7/27 2007/10/29
(Segment mode) SYMBOL VDD GND LGND VSS V0L, V0R V12L, V12R V43L, V43R
DI7-DI0
XCK LP L/R
/DISPOFF
FR
MD S/C
ElO1, EIO2
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ST8016T
Y1 -Y160
non-selected after 160 bits of data have been read. LCD drive output pins Y Corresponding directly to each bit of the data latch, one level (V0, V12 or V43) is selected and output. Y Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
(Common mode) SYMBOL VDD GND LGND VSS V0L, V0R V12L, V12R V43L, V43R
ElO1
EIO2
LP L/R
/DISPOFF
FR
MD
DI7
FUNCTION Logic system power supply pin Y Connected to +2.5 to +5.5 V. Ground pin Logic system power ground pin Y Do not short LGND with GND and Vss by ITO on LCD panel Y Connect it to GND on PCB or FPC. Connect to GND by ITO on LCD panel. Bias power supply pins for LCD drive voltage Y Normally use the bias voltages set by a resistor divider. Y Ensure that voltages are set such that VSS < V43 < V12 < V0. Y ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage that is assigned by specification for each power pin. Shift data input/output pin for bi-directional shift register Y Output pin when L/R is at LGND level "L', input pin when L/R is at VDD level "H". Y When L/R = H, ElO1 is used as input pin, it will be pulled down. Y When L/R = L, ElO1 is used as output pin, it won't be pulled down. Y Refer to section 7.2.2. Shift data input/output pin for bi-directional shift register Y Input pin when L/R is at LGND level "L", output pin when L/R is at VDD level "H". Y When L/R = L, EIO2 is used as input pin, it will be pulled down. Y When L/R = H, EIO2 is used as output pin, it won't be pulled down. Y Refer to section 7.2.2. Shift clock pulse input pin for bi-directional shift register Y * Data is shifted at the falling edge of the clock pulse. Input pin for selecting the shift direction of bi-directional shift register Y Data is shifted from Y160 to Y1 when set to LGND level "L", and data is shifted from Y1 to Y160 when set to VDD level "H". Y Refer to section 7.2.2. Control input pin for output of non-select level Y The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Y When set to LGND level "L", the LCD drive output pins (Y1-Y160) are set to level Vss. Y When set to "L", the contents of the shift register are reset to not reading data. When the /DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), and the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, the shift data is not read correctly. Y Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform Y The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Y Normally it inputs a frame inversion signal. Y The LCD drive output pins' output voltage levels can be set using the shift register output signal and the FR signal. Y Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. Mode selection pin Y When set to LGND level "L", single mode operation is selected; when set to VDD level "H" dual mode operation is selected. Y Refer to section 7.2.2. Dual mode data input pin Y According to the data shift direction of the data shift register, data can be input starting from the 81st bit. Page 8/27 2007/10/29
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ST8016T
S/C DI6-DI0 XCK Y1 -Y160
When the chip is used in dual mode, DI7 will be pulled down. When the chip is used in single mode, DI7 won't be pulled down(Connect to LGND or VDD, avoiding floating.). Y Refer to section 7.2.2. Segment mode/common mode selection pin Y When set to LGND level "L", common mode is set. Not used Y Connect DI6-DI0 to LGND or VDD, avoiding floating. Not used Y XCK is pulled down in common mode, so connect to LGND or open. LCD drive output pins Y Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or VSS) is selected and output. Y Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
7.2 7.2.1
Functional Operations Truth table
(Segment Mode) FR LATCH DATA /DISPOFF LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y160) L L H V43 L H H VSS H L H V12 H H H V0 X X L VSS (Common Mode) FR LATCH DATA /DISPOFF LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y160) L L H V43 L H H V0 H L H V12 H H H VSS X X L VSS NOTES: 1. VSS < V43 < V12 < V0 2. L : LGND (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care 3. "Don't care" should be fixed to "H" or "L", avoiding floating. 4. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. 5. Supply regular voltage that is assigned by specification for each power pin.
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7.2.2
Relationship between the display data and LCD drive output Pins
(Segment Mode) (a) 4-bit Parallel Input Mode MD L/R NUMBER OF CLOCKS DATA INPUT 40 CLOCK 39 CLOCK 38 CLOCK ... 3 CLOCK 2 CLOCK 1 CLOCK DI0 Y1 Y5 Y9 ... Y149 Y153 Y157 Dl1 Y2 Y6 Y10 ... Y150 Y154 Y158 Output Input DI2 Y3 Y7 Y11 ... Y151 Y155 Y159 DI3 Y4 Y8 Y12 ... Y152 Y156 Y160 DI0 Y160 Y156 Y152 ... Y12 Y8 Y4 Dl1 Y159 Y155 Y151 ... Y11 Y7 Y3 Input Output DI2 Y158 Y154 Y150 ... Y10 Y6 Y2 DI3 Y157 Y153 Y149 ... Y9 Y5 Y1 EIO1 EIO2 DATA NUMBER OF CLOCKS INPUT 20 CLOCK 19 CLOCK 18 CLOCK ... 3 CLOCK 2 CLOCK 1 CLOCK DI0 Y1 Y9 Y17 ... Y137 Y145 Y153 Dl1 Y2 Y10 Y18 ... Y138 Y146 Y154 DI2 Y3 Y11 Y19 ... Y139 Y147 Y155 DI3 Y4 Y12 Y20 ... Y140 Y148 Y156 Output Input DI4 Y5 Y13 Y21 Y141 Y149 Y157 DI5 Y6 Y14 Y22 Y142 Y150 Y158 DI6 Y7 Y15 Y23 Y143 Y151 Y159 DI7 Y8 Y16 Y24 Y144 Y152 Y160 DI0 Y160 Y152 Y144 ... Y24 Y16 Y8 Dl1 Y159 Y151 Y143 ... Y23 Y15 Y7 DI2 Y158 Y150 Y142 ... Y22 Y14 Y6 DI3 Y157 Y149 Y141 ... Y21 Y13 Y5 Input Output DI4 Y156 Y148 Y140 ... Y20 Y12 Y4 Dl5 Y155 Y147 Y139 ... Y19 Y11 Y3 DI6 Y154 Y146 Y138 ... Y18 Y10 Y2 DI7 Y153 Y145 Y137 ... Y17 Y9 Y1 EIO1 EIO2 L/R L H L H DATA TRANSFER DIRECTION Y160 Y1 Y1 Y160 Y160 Y81 Y80 Y1 Y1 Y80 Y81 Y160 EIO1 Output Input Output Input EIO2 Input Output Input Output DI7 X X Input Input
L
L
L
H
(b) MD
8-bit Parallel Input Mode L/R
H
L
H
H
(Common Mode) MD L (Single) H (Dual)
NOTES: 1. L : LGND (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care 2. "Don't care" should be fixed to "H" or "L", avoiding floating.
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7.2.3
(a)
Connection examples of plural segment drivers
When L/R = "L"
Top data Data flow
Last data
Y160
EIO2
Y1
EIO1 L/R DI7-DI0
Y160
EIO2
Y1
EIO1 L/R DI7-DI0
Y160
EIO2
Y1
EIO1 L/R DI7-DI0
XCK
XCK
XCK
MD
MD
MD
FR
FR
FR
LP
LP
LP
XCK LP MD FR DI7-DI0 8
LGND
(b)
When L/R = "H"
VDD
XCK LP MD FR DI7-DI0 XCK L/R LGND EIO1 EIO2 LP MD FR DI7-DI0 8 XCK L/R EIO1 EIO2 LP MD FR DI7-DI0 XCK L/R EIO1 EIO2 LP MD FR DI7-DI0
Y1
Top data
Y160
Data flow
Y1
Y160
Y1
Y160
Last data
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7.2.4
Timing chart of 4-device cascade connection of segment drivers
FR
LP
XCK
TOP DATA DI7 - DI0 n* 1 2 n* 1 2 n* 1 2 n* 1 2 n* 1
LAST DATA 2
device A
device B
device C
device D
EI (device A) EO (device A)
EO (device B)
EO (device C) *n = 40 in 4-bit parallel input mode *n = 20 in 8-bit parallel input mode
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7.2.5
(a)
Connection examples for plural common drivers
Single Mode (L/R = "L")
First
Last
Y160
FLM EIO2
Y1
EIO1 /DISPOFF
Y160
EIO2
Y1
EIO1 /DISPOFF
Y160
EIO2
Y1
EIO1 /DISPOFF
L/R
L/R
L/R
MD
MD
MD
DI7
DI7
DI7
LP
LP
LP
FR
FR
FR
LP LGND(V DD) LGND /DISPOFF FR
(b)
Single Mode (L/R = "H")
FR /DISPOFF V DD LGND LGND(V DD) LP /DISPOFF MD /DISPOFF DI7 LP DI7 LP LP FR L/R MD FR L/R MD FR L/R /DISPOFF DI7
FLM
EIO1
EIO2
EIO1
EIO2
EIO1
EIO2
Y1
Y160
Y1
Y160
Y1
Y160
First
Last
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ST8016T
(c)
Dual Mode (L/R = "L")
First
Last 1
First 2
Last 2
Y160
FLM1 EIO2
Y1
EIO1 /DISPOFF
Y160 Y81
EIO2
Y80
Y1
EIO1
Y160
EIO2
Y1
EIO1 /DISPOFF
/DISPOFF
L/R
L/R
L/R
MD
MD
MD
DI7
DI7
DI7
FR
FR
FR
LP
LP
LP
LP FLM2 LGND (V DD) V DD VSS /DISPOFF FR
(d)
Dual mode (L/R = "H")
FR /DISPOFF VDD LGND LGND (V DD) FLM2 LP DI7 LP DI7 LP LP FR L/R MD FR L/R MD FR L/R MD DI7 /DISPOFF /DISPOFF /DISPOFF
FLM1
EIO1
EIO2
EIO1
EIO2
EIO1
EIO2
Y1
Y160
Y1 Y80
Y81 Y160
Y1
Y160
First 1
Last 1 First 2
Last 2
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ST8016T
8
PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so a high current that may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating may permanently damage it. The details are as follows,
n
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When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power It is advisable to connect the serial resistor (4.7 to 50 ) or fuse to the LCD drive power V0 of the system as a current limiter. Set up a suitable value of the resistor in consideration of the display grade. And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on /DISPOFF function. After that, cancel the /DISPOFF function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level LGND on /DISPOFF function. Then disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here
VDD VDD LGND
VDD /DISPOFF LGND
V0 V0 GND
.
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage (1) Supply voltage (2) Input voltage SYMBOL VDD V0 V12 V43 VI APPLICABLE PINS VDD V0L, V0R V12L, V12R V43L, V43R DI7-DI0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, /DISPOFF RATING -0.3~ +7.0 -0.3 ~ +33.0 V0 -10~ V0 + 0.3 -0.3 ~ VSS + 10 -0.3 to VDD + 0.3 UNIT V V V V V NOTE
1,2
Storage temperature TSTG -45 to +125 C NOTES: 1. TA = +25 C 2. The applicable voltage on logic pins with respect to LGND, high voltage pins with VSS (0 V).
10
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE Supply voltage (1) VDD VDD +2.5 +5.5 V 1, 2 Supply voltage (2) V0 V0L, V0R +15.0 +30.0 V C Operating temperature TOPR -25 +70 NOTES: 1. The applicable voltage on logic pins with respect to LGND, high voltage pins with VSS (0 V). 2. Ensure that voltages are set such that VSS < V43 < Vl2 < V0.
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11
11.1
ELECTRICAL CHARACTERISTICS
DC Characteristics
(LGND =VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 15.0 to +30.0 V, TOPR = -25 to +70 C) SYMBOL CONDITIONS APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE VIL DI7-DI0, XCK, LP, L/R 0.2VDD V FR, MD, S/C, EIO1, EIO2, V Input "High" voltage VIH 0.8VDD /DISPOFF Output "Low" voltage V0L IOL = +0.4 mA +0.4 V EIO1, EIO2 Output "High" voltage V0H IOH = -0.4 mA VDD-0.4 V ILIL VI = LGND -10 A DI7-DI0, XCK, LP, L/R Input leakage current FR, MD, S/C, EIO1, EIO2, ILIH VI = VDD +10 A /DISPOFF | VON| Output resistance RON V0 = 30 V Y1-Y160 1.0 1.5 k =0.5V Standby current ISTB LGND+GND+VSS 50 A 1 Supply current (1) IDD1 VDD 2.0 mA 2 (Non-selection) Supply current (2) IDD2 VDD 7.0 mA 3 (Selection) Supply current (3) I0 V0L, V0R 0.9 mA 4 NOTES: 1. VDD = +5.0 V, V0 = +30.0 V, Vi = LGND. 2. VDD = +5.0 V, V0 = +30.0 V, fXCK = 20 MHz, no-load, El = VDD. The input data is turned over by data taking clock (4-bit parallel input mode). 3. VDD = +5.0 V, V0 = +30.0 V, fXCK = 20 MHz, no-load, El = LGND. The input data is turned over by data taking clock (4-bit parallel input mode). 4. VDD = +5.0 V, V0 = +30.0 V, fXCK = 20MHz, fLP = 20.8 kHz, fFR = 80 Hz, no-load. The input data is turned over by data taking clock (4-bit parallel input mode). (Common Mode) PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input leakage current Input pull-down current Output resistance (LGND =VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 15.0 to +30.0 V, TOPR = -25 to +70 C) SYMBOL CONDITIONS APPLICABL E PINS MIN. TYP. MAX. UNIT NOTE VIL DI7-DI0, XCK, LP, L/R 0.2VDD V FR, MD, S/C, EIO1, VIH V 0.8VDD EIO2, /DISPOFF V0L IOL = +0.4 mA +0.4 V EIO1, EIO2 V0H IOH = -0.4 mA VDD-0.4 V DI7-DI0, XCK, LP, L/R -10.0 A ILIL VI = LGND FR, MD, S/C, EIO1, EIO2, /DISPOFF DI6-DI0, LP, L/R, FR, +10.0 A ILIH VI = VDD MD, S/C, /DISPOFF IPD VI = VDD DI7, XCK, EIO1, EIO2 100 A | VON| RON V0 = 30 V Y1-Y160 1.0 1.5 k =0.5V ISPD LGND+GND+VSS 50 A 1 IDD VDD 80 A 2 I0 V0L, V0R 130 A 2
(Segment Mode) PARAMETER Input "Low" voltage
Standby current Supply current (1) Supply current (2) NOTES: 1. VDD = +5.0 V, V0 = +30.0 V, VI = LGND 2. VDD = +5.0 V, V0 = +30.0 V, fLP =20.8 kHz, fFR = 80 Hz, 1/320 duty operation, no-load.
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ST8016T
11.2
AC Characteristics
(Segment Mode 1) (LGND =VSS = 0 V, VDD = +2.5 to +3.0 V, V0 = + 15.0 to +30.0 V, TOPR = -25 10+70 C) PARAMETER SYMBOL CONDITIONS MIN TYP. MAX. UNIT NOTE Shift clock period tWCK tR,tF 11ns 125 ns 1 Shift clock "H" pulse width tWCKH 51 ns Shift clock "L" pulse width tWCKL 51 ns Data setup time tDS 30 ns Data hold time tDH 40 ns Latch pulse "H" pulse width tWLPH 51 ns Shift clock rise to latch pulse rise time tLD 0 ns Shift clock fall to latch pulse fall time tSL 51 ns Latch pulse rise to shift clock rise time tLS 51 ns Latch pulse fall to shift clock fall time tLH 51 ns Enable setup time tS 36 ns Input signal rise time tR 50 ns 2 Input signal fall time tF 50 ns 2 DISPOFF removal time tSD 100 ns DISPOFF "L" pulse width tWDL 1.2 s Output delay time (1) tD CL = 15 pF 78 ns Output delay time (2) tPD1, t PD2 CL = 15 pF 1.2 s Output delay time (3) t PD3 CL = 15 pF 1.2 s NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. (Segment Mode 2) (LGND =VSS = 0 V, VDD = +5.0 0.5 V, V0 = + 15.0 to +30.0 V, TOPR = -25 to +70 C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Shift clock period tWCK tR,tF 10ns 66 ns 1 Shift clock "H" pulse width tWCKH 23 ns Shift clock "L" pulse width tWCKL 23 ns Data setup time tDS 15 ns Data hold time tDH 23 ns Latch pulse "H" pulse width tWLPH 30 ns Shift clock rise to latch pulse rise time tLD 0 ns Shift clock fall to latch pulse fall time tSL 50 ns Latch pulse rise to shift clock rise time tLS 30 ns Latch pulse fall to shift clock fall time tLH 30 ns Enable setup time tS 15 ns Input signal rise time tR 50 ns 2 Input signal fall time tF 50 ns 2 DISPOFF removal time tSD 100 ns DISPOFF "L" pulse width tWDL 1.2 s Output delay time (1) tD CL = 15 pF 41 ns Output delay time (2) tPD1, t PD2 CL = 15 pF 1.2 s Output delay time (3) t PD3 CL = 15 pF 1.2 s NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
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ST8016T
(Segment Mode 3) (LGND =VSS = 0 V, VDD = +3.0 to +4.5 V, V0 = + 15.0 to +30.0 V, TOPR = -25 10+70 C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE Shift clock period tWCK tR,tF 10ns 82 ns 1 Shift clock "H" pulse width tWCKH 28 ns Shift clock "L" pulse width tWCKL 28 ns Data setup time tDS 20 ns Data hold time tDH 23 ns Latch pulse "H" pulse width tWLPH 30 ns Shift clock rise to latch pulse rise time tLD 0 ns Shift clock fall to latch pulse fall time tSL 51 ns Latch pulse rise to shift clock rise time tLS 30 ns Latch pulse fall to shift clock fall time tLH 30 ns Enable setup time tS 15 ns Input signal rise time tR 50 ns 2 Input signal fall time tF 50 ns 2 DISPOFF removal time tSD 100 ns DISPOFF "L" pulse width tWDL 1.2 s Output delay time (1) tD CL = 15 pF 57 ns Output delay time (2) tPD1, t PD2 CL = 15 pF 1.2 s Output delay time (3) t PD3 CL = 15 pF 1.2 s NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. (Common Mode) (LGND =VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = +15.0 to +30.0 V, TOPR = -25 to +70 C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Shift clock period tWLP tR,tF 20ns 250 ns VDD = +5.0 0.5V 15 ns Shift clock "H" pulse width tWLPH VDD = +2.5+ 4.5V 30 ns Data setup time tSU 30 ns Data hold time tH 50 ns Input signal rise time tR 50 ns Input signal fall time tF 50 ns DISPOFF removal time tSD 100 ns DISPOFF "L" pulse width tWDL 1.2 s Output delay time (1) tDL CL = 15 pF 200 ns Output delay time (2) tPD1, t PD2 CL = 15 pF 1.2 s Output delay time (3) t PD3 CL = 15 pF 1.2 s
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ST8016T
11.3
Timing Chart of Segment Mode
tWLPH
LP
tLD tLS tSL tLH tWCKH tWCKL
XCK
tR tWCK tF tDS tDH
DI7 - DI0
LAST DATA
TOP DATA
tWDL
tSD
DISPOFF
LP XCK n*
1 tS
2
EI tD EO *n = 40 in 4-bit parallel input mode *n = 20 in 8-bit parallel input mode
FR tPD1 LP tPD2 DISPOFF tPD3 Y1 - Y160
Fig. 8 Timing Characteristics (3)
Preliminary Ver 0.12
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ST8016T
11.4
Timing Chart of Common Mode
tWLP
LP
tR
tWLPH tSU
tF tH
EIO2
tDL
EIO1
tWDL
DISPOFF
tSD
FR tPD1 LP tPD2 DISPOFF tPD3 Y1 - Y160
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ST8016T
12
12.1
VEE
APPLICATION CIRCUIT
Application Circuit for Module
5
EIO2 MD S/C L/R DI0~DI7 EIO1 Y1~Y160 FR LP /DISPOFF XCK
4.7~50
Power GND
160 X 160 DOT LCD PANEL
ST8016T Y1~Y160
10
FR /DISPOFF LP XCK VSS VDD FLM AC LP /DISPOFF XCK XD0~XD7
5
DI0~DI7 EIO1 CONTROLLER
EIO2
S/C
MD
L/R
ST8016T
8
Preliminary Ver 0.12
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ST8016T
13
PAD DIAGRAM
Y80 DUMMY Y81 DUMMY Y1 Y160 DUMMY
141
139
Unit: um PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Preliminary Ver 0.12
220 221
59 60
DUMMY
GND GND DUMMY
S/C VDD VDD L/R LGND LGND
DUMMY
DUMMY DI5 DI4 DI3 DI2 DI1 DI0
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY /DISPOFF XCK DI7 DI6 DUMMY
GND GND
DUMMY
LGND LGND MD FR
EIO2
EIO1
LP
Name V0L V0L V0L V0L V12L V12L V34L V34L VSS VSS GND GND DUMMY LGND LGND L/R VDD VDD S/C EIO2 DUMMY DI0 DI1 DI2 DI3 DI4 DI5 DUMMY DUMMY DUMMY DUMMY
X -4357.250 -4357.250 -4357.250 -4357.250 -4357.250 -4357.250 -4357.250 -4357.250 -4357.250 -4357.250 -4190.000 -4065.200 -3906.700 -3600.500 -3493.050 -3357.200 -3223.550 -3116.100 -2978.650 -2635.050 -2264.675 -1872.100 -1710.800 -1546.200 -1384.900 -1220.300 -1059.000 -883.300 -527.800 -161.075 228.825
Y PIN# 266.850 32 207.550 33 148.250 34 88.950 35 29.650 36 -29.650 37 -88.950 38 -148.250 39 -207.550 40 -266.850 41 -263.150 42 -263.150 43 -209.050 44 -263.150 45 -263.150 46 -263.100 47 -263.150 48 -263.150 49 -263.100 50 -263.100 51 -263.100 52 -263.100 53 -263.100 54 -263.100 55 -263.100 56 -263.100 57 -263.100 58 -263.100 59 -224.400 60 -227.675 61 -217.725 62
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Name DUMMY DUMMY DUMMY DI6 DI7 XCK /DISPOFF DUMMY LP EIO1 FR MD LGND LGND DUMMY GND GND VSS VSS V34R V34R V12R V12R V0R V0R V0R V0R DUMMY Y1 Y2 Y3
X 614.425 878.050 1264.175 1425.350 1586.650 1751.250 1912.550 2116.875 2509.450 2845.600 3195.300 3356.600 3493.050 3600.500 3906.700 4065.200 4190.000 4357.250 4357.250 4357.250 4357.250 4357.250 4357.250 4357.250 4357.250 4357.250 4357.250 4237.000 4187.000 4135.000 4083.000
Y -217.725 -220.475 -263.100 -263.100 -263.100 -263.100 -263.100 -263.100 -263.100 -263.100 -263.100 -263.100 -263.150 -263.150 -209.050 -263.150 -263.150 -266.850 -207.550 -148.250 -88.950 -29.650 29.650 88.950 148.250 207.550 266.850 250.100 250.100 250.100 250.100
2007/10/29
ST8016T
63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110
Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51
4031.000 3979.000 3927.000 3875.000 3823.000 3771.000 3719.000 3667.000 3615.000 3563.000 3511.000 3459.000 3407.000 3355.000 3303.000 3251.000 3199.000 3147.000 3095.000 3043.000 2991.000 2939.000 2887.000 2835.000 2783.000 2731.000 2679.000 2627.000 2575.000 2523.000 2471.000 2419.000 2367.000 2315.000 2263.000 2211.000 2159.000 2107.000 2055.000 2003.000 1951.000 1899.000 1847.000 1795.000 1743.000 1691.000 1639.000 1587.000
250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100
111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158
Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 Y75 Y76 Y77 Y78 Y79 Y80 DUMMY Y81 Y82 Y83 Y84 Y85 Y86 Y87 Y88 Y89 Y90 Y91 Y92 Y93 Y94 Y95 Y96 Y97 Y98
1535.000 1483.000 1431.000 1379.000 1327.000 1275.000 1223.000 1171.000 1119.000 1067.000 1015.000 963.000 911.000 859.000 807.000 755.000 703.000 651.000 599.000 547.000 495.000 443.000 391.000 339.000 287.000 235.000 183.000 131.000 79.000 0.000 -79.000 -131.000 -183.000 -235.000 -287.000 -339.000 -391.000 -443.000 -495.000 -547.000 -599.000 -651.000 -703.000 -755.000 -807.000 -859.000 -911.000 -963.000
250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100
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Preliminary Ver 0.12
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ST8016T
159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190
Y99 Y100 Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117 Y118 Y119 Y120 Y121 Y122 Y123 Y124 Y125 Y126 Y127 Y128 Y129 Y130
-1015.000 -1067.000 -1119.000 -1171.000 -1223.000 -1275.000 -1327.000 -1379.000 -1431.000 -1483.000 -1535.000 -1587.000 -1639.000 -1691.000 -1743.000 -1795.000 -1847.000 -1899.000 -1951.000 -2003.000 -2055.000 -2107.000 -2159.000 -2211.000 -2263.000 -2315.000 -2367.000 -2419.000 -2471.000 -2523.000 -2575.000 -2627.000
250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100
191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221
Y131 Y132 Y133 Y134 Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 DUMMY
-2679.000 -2731.000 -2783.000 -2835.000 -2887.000 -2939.000 -2991.000 -3043.000 -3095.000 -3147.000 -3199.000 -3251.000 -3303.000 -3355.000 -3407.000 -3459.000 -3511.000 -3563.000 -3615.000 -3667.000 -3719.000 -3771.000 -3823.000 -3875.000 -3927.000 -3979.000 -4031.000 -4083.000 -4135.000 -4187.000 -4237.000
250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100 250.100
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ST8016T
13.1
Gold Bump size (unit: um) X Y Area (um2) 1~10,49~58 87.50 44.30 3876.2500 11,12,47,48 109.80 42.30 4644.5400 13,46 160.20 33.30 5334.6600 1415,17,18,44,45 92.50 42.30 3912.7500 16,19,20,22~27,35~38,40~43 131.30 42.40 5567.1200 21,39 152.35 42.40 6459.6400 28 165.80 42.40 7029.9200 29 94.30 44.40 4186.9200 30 103.85 37.85 3930.7225 31,32 85.65 57.75 4946.2875 33 117.20 52.25 6123.7000 34 136.75 42.40 5798.2000 59,221 33.00 81.00 2673.0000 60~139,141~220 37.00 81.00 2997.0000 140 91.00 81.00 7371.0000 Wafer thickness = 48020um, Bump pad height (pad 1~215) = 15um, strength=30g Pad No.
Preliminary Ver 0.12
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ST8016T
14
REVISION
REVISION 0.10 0.11 0.12 DESCRIPTION First release Change Max. operating voltage to +30.0V Change Standby Current Application Pin to LGND+GND+VSS Modify operating temperature to 70C PAGE 1-27 1-27 16-19 DATE 2006/12/11 2007/04/20 2007/10/29
The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix.
Preliminary Ver 0.12
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2007/10/29

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